The invention is directed to a method for manufacturing contacts between interconnects contained in wiring levels arranged above one another in an integrated circuit.
In many families of integrated circuits, the linking of the individual elements or of entire modules of an integrated circuit occurs with a wiring on two or more levels. A separating insulation layer lies between these levels. The levels are connected via contacts through via holes in the separating insulation layer. These contacts are called vias.
Continuing miniaturization given a simultaneous increase of the current density in the metallic interconnects of integrated circuits requires vias that are largely filled with conductive material.
Various ways of producing via holes as well as filling these via holitle, R. H. Wilson et al, J. Electrochem., Soc.: Accelerated Brief Communication, page 1867 (July 1987); H. P. W. Hey et al Proc. IEDM, 3.2, page 50 (1986); E. R. Sirkin, I. A. Blech, J. Electrochem. Soc., Vol. 131, No. 1, p. 123 (1983), all incorporated herein by reference).
One way is to apply an insulation layer after the deposition and structuring of the lower metal layer, this insulation layer serving the purpose of separating the two wiring levels. This insulation layer is generally a plasma oxide layer that has a planarizing effect due to special methods. The planarizing is necessary in order to guarantee the necessary deactivation of the topology for the upper metal level. Via holes are produced in the insulation layer by reactive ion etching. The filling of the via holes occurs, for example, via a surface-wide tungsten deposition having a following etch-back step, or occurs with a selective tungsten deposition.
Such a method is disclosed in E. Bertagnolli et al, Journal de Physique, Vol. 49, C 4 (1988), pages 179 through 182, incorporated herein.
It is not assured in this method that the via holes through the conductive material will be completely filled. This can potentially lead to an undesired cross-sectional diminution of the interconnects. A mask that must be adjusted relative to a lower level is necessary for producing the via holes. The mask must be structured and adjusted such that a reliable overlap between interconnect and via hole, i.e. with the contact as well, is guaranteed. This overlap represents a considerable contribution to the size of the wiring grid in the lower metal level and therefore lowers the obtainable packing density.
Another way is what is referred to as the pillar technique which, for example, is described in E. R. Sirkin, I. A. Blech, J. Electrochem. Soc., Vol. 131, No. 1, page 123 (1983) incorporated herein by reference. The conductive material that is later intended to fill the vias is thus already deposited and structured before the insulation layer. This structuring occurs via a mask that corresponds to a complementary via mask. Subsequently, the insulation layer is deposited onto the surface and is etched back until the upper cover surfaces of the raised metal regions are exposed. The raised metal regions are referred to as pillars. This method assures a complete filling of the via holes. It is also assured that an adequate layer thickness above conductive layers lying therebelow is established at the edges of the insulation layers. The disadvantage of mask adjustment, however, remains.